/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-14 16:29:52
 *
 */


#ifndef ANLG_PHY_G3_SIDE_H
#define ANLG_PHY_G3_SIDE_H

#define CTL_BASE_ANLG_PHY_G3_SIDE 0x323B0000


#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TEST_PIN           ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x0000 )
#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_UTMI_CTL1          ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x0004 )
#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BATTER_PLL         ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x0008 )
#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_UTMI_CTL2          ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x000C )
#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TRIMMING           ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x0010 )
#define REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_PHY_BIST_TEST      ( CTL_BASE_ANLG_PHY_G3_SIDE + 0x0014 )

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TEST_PIN */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TESTCLK            BIT(18)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TESTDATAIN(x)      (((x) & 0xFF) << 10)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TESTADDR(x)        (((x) & 0xF) << 6)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TESTDATAOUTSEL     BIT(5)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BIST_MODE(x)       (((x) & 0x1F))

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_UTMI_CTL1 */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_DATABUS16_8        BIT(24)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BYPASS_DRV_DP      BIT(23)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BYPASS_DRV_DM      BIT(22)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BYPASS_IN_DP       BIT(20)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BYPASS_OUT_DM      BIT(17)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_VBUSVLDEXT         BIT(16)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_RESERVED(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BATTER_PLL */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_REXTENABLE         BIT(1)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_DMPULLUP           BIT(0)

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_UTMI_CTL2 */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TXBITSTUFFENABLE   BIT(1)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TXBITSTUFFENABLEH  BIT(0)

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TRIMMING */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNEHSAMP(x)       (((x) & 0x3) << 27)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TFREGRES(x)        (((x) & 0x3F) << 21)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TFHSRES(x)         (((x) & 0x1F) << 16)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNERISE(x)        (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNEOTG(x)         (((x) & 0x7) << 11)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNEDSC(x)         (((x) & 0x3) << 9)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNESQ(x)          (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNEEQ(x)          (((x) & 0x7) << 2)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_TUNEPLLS(x)        (((x) & 0x3))

/* REG_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_PHY_BIST_TEST */

#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BISTRAM_EN         BIT(1)
#define BIT_ANLG_PHY_G3_SIDE_ANALOG_USB20_USB20_BIST_MODE_EN       BIT(0)


#endif /* ANLG_PHY_G3_SIDE_H */


